Mmc1Mapper.java

package com.rox.cartridge;

import com.rox.mem.RAM;

import java.util.LinkedHashMap;
import java.util.Map;

import static com.rox.ByteUtil.BYTE_MASK;

/**
 * iNES mapper 1 (MMC1). Every write to {@code $8000-$FFFF} feeds one bit (the value's bit 0) into a
 * 5-bit serial shift register, LSB first; on the 5th write, the assembled 5-bit value latches into
 * one of four internal registers, chosen by which address range that 5th write landed in:
 * {@code $8000-$9FFF} control, {@code $A000-$BFFF} CHR bank 0, {@code $C000-$DFFF} CHR bank 1,
 * {@code $E000-$FFFF} PRG bank. A write with bit 7 set doesn't shift at all - it immediately resets
 * the shift register and forces the control register's PRG bank mode to 3 (switch $8000, fix the
 * last bank at $C000), matching real hardware's power-on/reset state.
 *
 * PRG-ROM bank modes (control register bits 2-3): 0 and 1 both mean "switch a 32KB bank at $8000"
 * (the PRG bank register's bit 0 is ignored - the whole window moves as one 32KB unit); 2 fixes bank
 * 0 at $8000 and switches a 16KB bank at $C000; 3 switches a 16KB bank at $8000 and fixes the last
 * bank at $C000 (the reset state). 8KB PRG-RAM at $6000-$7FFF, always writable - this codebase
 * doesn't model the PRG-RAM chip-enable bit some MMC1 revisions (B2+) add to the PRG bank register.
 *
 * CHR (control register bit 4, {@link #CHR_MODE_BIT}): 0 = 8KB mode, one bank switched by
 * {@link #chrBank0Register()} with its bit 0 ignored (the whole 8KB window moves as one unit,
 * mirroring how PRG bank modes 0/1 ignore the PRG bank register's own bit 0); 1 = 4KB mode, two
 * independently-switched 4KB banks, one per CHR bank register. CHR-RAM boards (no CHR-ROM in the
 * file) get a single fixed 8KB RAM bank instead - real MMC1+CHR-RAM boards don't bank CHR-RAM either,
 * so the bank registers are simply ignored in that case. Mirroring is read dynamically from the
 * control register's low 2 bits on every call (0/1 = fixed single-screen lower/upper, 2 = vertical,
 * 3 = horizontal) - this overrides the iNES header's mirroring bit, real MMC1 hardware behaviour.
 *
 * Simplifications: the extended &gt;256KB SUROM/SOROM addressing scheme, which repurposes CHR bank
 * register bits as extra PRG bank bits, isn't modeled - not needed for any ROM this codebase
 * currently loads.
 */
public final class Mmc1Mapper implements Mapper {
    private static final int PRG_RAM_SIZE = 0x2000;
    private static final int PRG_ROM_START_ADDRESS = 0x8000;
    private static final int PRG_BANK_SIZE = 0x4000;
    private static final int CHR_BANK_0_START_ADDRESS = 0xA000;
    private static final int CHR_BANK_1_START_ADDRESS = 0xC000;
    private static final int PRG_BANK_REGISTER_START_ADDRESS = 0xE000;
    private static final int CHR_WINDOW_SIZE = 0x2000;
    private static final int CHR_BANK_4KB_SIZE = 0x1000;
    private static final int CHR_MODE_BIT = 0x10;
    private static final int CHR_BANK_NUMBER_MASK = 0x1F;
    private static final int MIRRORING_MODE_MASK = 0x03;

    private static final int RESET_BIT = 0x80;
    private static final int SHIFTS_PER_LATCH = 5;
    private static final int RESET_PRG_BANK_MODE_BITS = 0x0C;

    private static final int PRG_BANK_MODE_SHIFT = 2;
    private static final int PRG_BANK_MODE_MASK = 0x03;
    private static final int PRG_BANK_MODE_SWITCH_32KB_HIGH = 1;
    private static final int PRG_BANK_MODE_FIX_FIRST = 2;
    private static final int PRG_BANK_NUMBER_MASK = 0x0F;

    private final byte[] prgRom;
    private final RAM prgRam = new RAM(PRG_RAM_SIZE, "PRG-RAM");
    private final ChrMemory chr;

    private int shiftRegister;
    private int shiftCount;

    private int controlRegister = RESET_PRG_BANK_MODE_BITS; //power-on: PRG mode 3
    private int chrBank0Register;
    private int chrBank1Register;
    private int prgBankRegister;

    public Mmc1Mapper(final INesRom rom){
        this.prgRom = rom.prgRom();
        if (prgRom.length == 0){
            throw new IllegalArgumentException("MMC1 requires at least one 16KB PRG-ROM bank");
        }
        this.chr = ChrMemory.of(rom, CHR_WINDOW_SIZE);
    }

    /** Contract: only ever called with {@code address} in {@code $6000-$FFFF} (see class Javadoc). */
    @Override
    public int read(final int address){
        if (address >= PRG_ROM_START_ADDRESS){
            return prgRom[prgRomOffset(address)] & BYTE_MASK;
        }
        return prgRam.read(address);
    }

    /** Contract: only ever called with {@code address} in {@code $6000-$FFFF} (see class Javadoc). */
    @Override
    public void write(final int address, final int value){
        if (address < PRG_ROM_START_ADDRESS){
            prgRam.write(address, value);
            return;
        }
        if ((value & RESET_BIT) != 0){
            shiftRegister = 0;
            shiftCount = 0;
            controlRegister |= RESET_PRG_BANK_MODE_BITS;
            return;
        }
        shiftRegister |= (value & 1) << shiftCount;
        shiftCount++;
        if (shiftCount == SHIFTS_PER_LATCH){
            latch(address, shiftRegister);
            shiftRegister = 0;
            shiftCount = 0;
        }
    }

    private void latch(final int address, final int value){
        if (address < CHR_BANK_0_START_ADDRESS){
            controlRegister = value;
        } else if (address < CHR_BANK_1_START_ADDRESS){
            chrBank0Register = value;
        } else if (address < PRG_BANK_REGISTER_START_ADDRESS){
            chrBank1Register = value;
        } else {
            prgBankRegister = value;
        }
    }

    /**
     * <ul>
     * <li>$8000-$FFFF is a fixed 32KB CPU window, but MMC1 PRG-ROM can be up to 512KB.</li>
     * </ul>
     * The extra ROM doesn't fit in the window, so the game writes to a bank-select register (via the 5-bit
     * shift-register protocol you can see in write()/latch()) to say make a given chunk of the ROM
     * visible in the window.
     *
     * @param address to translate from CPU 32KB addressable size
     * @return address in addressable 512KB based on state of bank-select register state
     */
    private int prgRomOffset(final int address){
        final int windowOffset = address - PRG_ROM_START_ADDRESS; //0..0x7FFF
        final int totalBanks = prgRom.length / PRG_BANK_SIZE;
        final int prgBankMode = (controlRegister >> PRG_BANK_MODE_SHIFT) & PRG_BANK_MODE_MASK;
        final int bankNumber = prgBankRegister & PRG_BANK_NUMBER_MASK;

        if (prgBankMode <= PRG_BANK_MODE_SWITCH_32KB_HIGH){
            final int bank32 = (bankNumber >> 1) % Math.max(1, totalBanks / 2);
            //mirrors a single-bank (16KB) ROM across the 32KB window, same as NromMapper's own
            //16KB-bank mirroring - a lone-bank MMC1 image is nonstandard but shouldn't crash
            return (bank32 * (PRG_BANK_SIZE * 2) + windowOffset) % prgRom.length;
        }
        if (windowOffset < PRG_BANK_SIZE){
            final int bank = prgBankMode == PRG_BANK_MODE_FIX_FIRST ? 0 : bankNumber % totalBanks;
            return bank * PRG_BANK_SIZE + windowOffset;
        }
        final int bank = prgBankMode == PRG_BANK_MODE_FIX_FIRST ? bankNumber % totalBanks : totalBanks - 1;
        return bank * PRG_BANK_SIZE + (windowOffset - PRG_BANK_SIZE);
    }

    @Override
    public int readChr(final int address){
        return chr.read(chrOffset(address));
    }

    /**
     * This is a no-op if Chr is ROM/Read-Only
     */
    @Override
    public void writeChr(final int address, final int value){
        chr.write(chrOffset(address), value);
    }

    /** CHR-RAM is one fixed 8KB bank (see class doc); only CHR-ROM is banked. */
    private int chrOffset(final int address){
        return chr.isRam() ? address & (CHR_WINDOW_SIZE - 1) : chrRomOffset(address);
    }

    /**
     * <ul>
     * <li>$0000-$1FFF is a fixed 8KB PPU window, but CHR-ROM can be up to 128KB.</li>
     * </ul>
     * The extra ROM doesn't fit in the window, so the game writes to a bank-select register (via the 5-bit
     * shift-register protocol you can see in write()/latch()) to say make a given chunk of the ROM
     * visible in the window.
     *
     * @param address to translate from PPU 8KB addressable size
     * @return address in addressable 128KB based on state of bank-select register state
     */
    private int chrRomOffset(final int address){
        final boolean fourKbMode = (controlRegister & CHR_MODE_BIT) != 0;
        final int totalFourKbBanks = chr.size() / CHR_BANK_4KB_SIZE;
        if (!fourKbMode){
            final int bank8kb = (chrBank0Register >> 1) % Math.max(1, totalFourKbBanks / 2);
            return (bank8kb * CHR_WINDOW_SIZE + address) % chr.size();
        }
        final int bankRegister = address < CHR_BANK_4KB_SIZE ? chrBank0Register : chrBank1Register;
        final int bank = (bankRegister & CHR_BANK_NUMBER_MASK) % totalFourKbBanks;
        return (bank * CHR_BANK_4KB_SIZE + (address & (CHR_BANK_4KB_SIZE - 1))) % chr.size();
    }

    @Override
    public Mirroring nametableMirroring(){
        return switch (controlRegister & MIRRORING_MODE_MASK){
            case 0 -> Mirroring.SINGLE_SCREEN_LOWER;
            case 1 -> Mirroring.SINGLE_SCREEN_UPPER;
            case 2 -> Mirroring.VERTICAL;
            default -> Mirroring.HORIZONTAL;
        };
    }

    int controlRegister(){
        return controlRegister;
    }

    int chrBank0Register(){
        return chrBank0Register;
    }

    int chrBank1Register(){
        return chrBank1Register;
    }

    int prgBankRegister(){
        return prgBankRegister;
    }

    @Override
    public Map<String, String> debugState(){
        final Map<String, String> state = new LinkedHashMap<>();
        state.put("Control", String.format("$%02X", controlRegister));
        state.put("CHR bank 0", String.format("$%02X", chrBank0Register));
        state.put("CHR bank 1", String.format("$%02X", chrBank1Register));
        state.put("PRG bank", String.format("$%02X", prgBankRegister));
        return state;
    }

    @Override
    public int[] prgRam(){
        return prgRam.snapshot();
    }

    @Override
    public void restorePrgRam(final int[] prgRam){
        this.prgRam.restore(prgRam);
    }

    @Override
    public MapperSnapshot snapshot(){
        return new Mmc1MapperSnapshot(prgRam.snapshot(), chr.snapshot(), shiftRegister, shiftCount,
                controlRegister, chrBank0Register, chrBank1Register, prgBankRegister);
    }

    @Override
    public void checkRestorable(final MapperSnapshot snapshot){
        final Mmc1MapperSnapshot mmc1 = SnapshotArrays.expect(snapshot, Mmc1MapperSnapshot.class);
        prgRam.checkRestorable(mmc1.prgRam());
        chr.checkRestorable(mmc1.chrRam());
    }

    @Override
    public void restore(final MapperSnapshot snapshot){
        checkRestorable(snapshot);
        final Mmc1MapperSnapshot mmc1 = (Mmc1MapperSnapshot) snapshot;
        prgRam.restore(mmc1.prgRam());
        chr.restore(mmc1.chrRam());
        shiftRegister = mmc1.shiftRegister();
        shiftCount = mmc1.shiftCount();
        controlRegister = mmc1.controlRegister();
        chrBank0Register = mmc1.chrBank0Register();
        chrBank1Register = mmc1.chrBank1Register();
        prgBankRegister = mmc1.prgBankRegister();
    }
}






















































Active mutators

CONDITIONALS_BOUNDARY
EMPTY_RETURNS
FALSE_RETURNS
INCREMENTS
INVERT_NEGS
MATH
NEGATE_CONDITIONALS
NULL_RETURNS
PRIMITIVE_RETURNS
TRUE_RETURNS
VOID_METHOD_CALLS

Tests examined

com.rox.cartridge.MapperSnapshotTest.[engine:junit-jupiter]/[class:com.rox.cartridge.MapperSnapshotTest]/[method:restoreRejectsAnotherBoardsSnapshot()] (1 ms)
com.rox.cartridge.MapperSnapshotTest.[engine:junit-jupiter]/[class:com.rox.cartridge.MapperSnapshotTest]/[test-template:rejectedRestoreChangesNothingWhicheverArrayIsWrong(java.lang.String, java.lang.String)]/[test-template-invocation:#3] (0 ms)
com.rox.cartridge.MapperSnapshotTest.[engine:junit-jupiter]/[class:com.rox.cartridge.MapperSnapshotTest]/[test-template:rejectedRestoreChangesNothingWhicheverArrayIsWrong(java.lang.String, java.lang.String)]/[test-template-invocation:#4] (0 ms)
com.rox.cartridge.MapperSnapshotTest.[engine:junit-jupiter]/[class:com.rox.cartridge.MapperSnapshotTest]/[method:mmc1RoundTripsEveryRegisterIncludingAPartFilledShiftRegister()] (1 ms)
com.rox.cartridge.MapperSnapshotTest.[engine:junit-jupiter]/[class:com.rox.cartridge.MapperSnapshotTest]/[method:restoredMmc1FinishesThePartFilledWriteTheSameWayTheOriginalDoes()] (1 ms)
com.rox.cartridge.MapperSnapshotTest.[engine:junit-jupiter]/[class:com.rox.cartridge.MapperSnapshotTest]/[test-template:checkRestorableRejectsWhicheverArrayIsWrong(java.lang.String, java.lang.String)]/[test-template-invocation:#3] (0 ms)
com.rox.cartridge.MapperSnapshotTest.[engine:junit-jupiter]/[class:com.rox.cartridge.MapperSnapshotTest]/[test-template:checkRestorableRejectsWhicheverArrayIsWrong(java.lang.String, java.lang.String)]/[test-template-invocation:#4] (0 ms)
com.rox.cartridge.MapperSnapshotTest.[engine:junit-jupiter]/[class:com.rox.cartridge.MapperSnapshotTest]/[method:checkRestorableAcceptsAMatchingSnapshotAndRejectsAMismatchedOneWithoutChangingAnything()] (1 ms)
com.rox.cartridge.Mmc1MapperTest.[engine:junit-jupiter]/[class:com.rox.cartridge.Mmc1MapperTest]/[method:prgBankMode2FixesFirstBankAndSwitchesSecondWindow()] (0 ms)
com.rox.cartridge.Mmc1MapperTest.[engine:junit-jupiter]/[class:com.rox.cartridge.Mmc1MapperTest]/[method:prgBankMode3SwitchesFirstWindowAndFixesLastBankAtSecondWindow()] (0 ms)
com.rox.cartridge.Mmc1MapperTest.[engine:junit-jupiter]/[class:com.rox.cartridge.Mmc1MapperTest]/[method:prgRamRoundTripsAcrossABankSwitch()] (0 ms)
com.rox.cartridge.Mmc1MapperTest.[engine:junit-jupiter]/[class:com.rox.cartridge.Mmc1MapperTest]/[method:prgBankMode3PreservesNonZeroOffsetWithinTheSwitchableWindow()] (7 ms)
com.rox.cartridge.RomLoaderTest.[engine:junit-jupiter]/[class:com.rox.cartridge.RomLoaderTest]/[method:mapperOneDispatchesToAWorkingMmc1Mapper()] (0 ms)
com.rox.cartridge.Mmc1MapperTest.[engine:junit-jupiter]/[class:com.rox.cartridge.Mmc1MapperTest]/[method:prgRamRoundTripsThroughRestore()] (0 ms)
com.rox.cartridge.Mmc1MapperTest.[engine:junit-jupiter]/[class:com.rox.cartridge.Mmc1MapperTest]/[method:prgBankMode0PicksTheCorrect32KbBankForABankNumberAboveHalfTheTotal()] (0 ms)
com.rox.cartridge.Mmc1MapperTest.[engine:junit-jupiter]/[class:com.rox.cartridge.Mmc1MapperTest]/[method:prgBankMode1AlsoSelects32KbBank()] (0 ms)
com.rox.cartridge.Mmc1MapperTest.[engine:junit-jupiter]/[class:com.rox.cartridge.Mmc1MapperTest]/[method:prgBankMode0DoesNotCrashOnASingleBankRomAndMirrorsIt()] (0 ms)
com.rox.cartridge.Mmc1MapperTest.[engine:junit-jupiter]/[class:com.rox.cartridge.Mmc1MapperTest]/[method:prgBankMode0Selects32KbBankIgnoringLowBitOfBankNumber()] (0 ms)
com.rox.cartridge.Mmc1MapperTest.[engine:junit-jupiter]/[class:com.rox.cartridge.Mmc1MapperTest]/[method:noChrBanksMeansWritableChrRamIgnoringBankRegisters()] (0 ms)
com.rox.cartridge.Mmc1MapperTest.[engine:junit-jupiter]/[class:com.rox.cartridge.Mmc1MapperTest]/[method:eachChrRamAddressHoldsItsOwnByteWhateverTheBankRegistersSay()] (0 ms)
com.rox.cartridge.Mmc1MapperTest.[engine:junit-jupiter]/[class:com.rox.cartridge.Mmc1MapperTest]/[method:chrEightKbModeSwitchesTheWholeWindowIgnoringTheBankRegistersLowBit()] (0 ms)
com.rox.cartridge.Mmc1MapperTest.[engine:junit-jupiter]/[class:com.rox.cartridge.Mmc1MapperTest]/[method:chrEightKbModeSelectsTheCorrectEightKbBankAmongSeveral()] (0 ms)
com.rox.cartridge.Mmc1MapperTest.[engine:junit-jupiter]/[class:com.rox.cartridge.Mmc1MapperTest]/[method:writesToChrRomAreNoOps()] (1 ms)
com.rox.cartridge.Mmc1MapperTest.[engine:junit-jupiter]/[class:com.rox.cartridge.Mmc1MapperTest]/[method:chrFourKbModeSelectsIndependentBanksForEachHalf()] (0 ms)
com.rox.cartridge.Mmc1MapperTest.[engine:junit-jupiter]/[class:com.rox.cartridge.Mmc1MapperTest]/[method:chrFourKbModeWrapsTheBankNumberModuloTheTotalBankCount()] (1 ms)
com.rox.cartridge.Mmc1MapperTest.[engine:junit-jupiter]/[class:com.rox.cartridge.Mmc1MapperTest]/[method:chrFourKbModeSwitchesEachHalfIndependently()] (0 ms)
com.rox.ApuTestRomIntegrationTest.[engine:junit-jupiter]/[class:com.rox.ApuTestRomIntegrationTest]/[method:combinedRomReportsExpectedStatus()] (2622 ms)
com.rox.cartridge.Mmc1MapperTest.[engine:junit-jupiter]/[class:com.rox.cartridge.Mmc1MapperTest]/[method:fifthWriteIsTheHighestBitOfTheLatchedValue()] (0 ms)
com.rox.cartridge.Mmc1MapperTest.[engine:junit-jupiter]/[class:com.rox.cartridge.Mmc1MapperTest]/[method:fiveWritesToLowRangeLatchTheControlRegister()] (0 ms)
com.rox.cartridge.Mmc1MapperTest.[engine:junit-jupiter]/[class:com.rox.cartridge.Mmc1MapperTest]/[method:fiveWritesToHighRangeLatchThePrgBankRegister()] (0 ms)
com.rox.cartridge.Mmc1MapperTest.[engine:junit-jupiter]/[class:com.rox.cartridge.Mmc1MapperTest]/[method:firstWriteIsTheLowestBitOfTheLatchedValue()] (0 ms)
com.rox.cartridge.Mmc1MapperTest.[engine:junit-jupiter]/[class:com.rox.cartridge.Mmc1MapperTest]/[method:resetBitAbortsAnInProgressSequenceAndForcesPrgMode3()] (0 ms)
com.rox.cartridge.Mmc1MapperTest.[engine:junit-jupiter]/[class:com.rox.cartridge.Mmc1MapperTest]/[method:resetBitDoesNotCountAsAShiftItself()] (0 ms)
com.rox.cartridge.Mmc1MapperTest.[engine:junit-jupiter]/[class:com.rox.cartridge.Mmc1MapperTest]/[method:fiveWritesToChrBank1RangeLatchChrBank1Register()] (0 ms)
com.rox.cartridge.Mmc1MapperTest.[engine:junit-jupiter]/[class:com.rox.cartridge.Mmc1MapperTest]/[method:resetSetsPrgBankModeBitsEvenWhenTheyWerePreviouslyClear()] (0 ms)
com.rox.cartridge.Mmc1MapperTest.[engine:junit-jupiter]/[class:com.rox.cartridge.Mmc1MapperTest]/[method:fiveWritesToChrBank0RangeLatchChrBank0Register()] (0 ms)
com.rox.cartridge.Mmc1MapperTest.[engine:junit-jupiter]/[class:com.rox.cartridge.Mmc1MapperTest]/[method:prgRamIsIndependentOfPrgRomBanking()] (0 ms)
com.rox.cartridge.Mmc1MapperTest.[engine:junit-jupiter]/[class:com.rox.cartridge.Mmc1MapperTest]/[method:mirroringControlBitsZeroAndOneMeanFixedSingleScreens()] (0 ms)
com.rox.cartridge.Mmc1MapperTest.[engine:junit-jupiter]/[class:com.rox.cartridge.Mmc1MapperTest]/[method:mirroringControlBitsTwoAndThreeMeanVerticalAndHorizontal()] (0 ms)
com.rox.cartridge.Mmc1MapperTest.[engine:junit-jupiter]/[class:com.rox.cartridge.Mmc1MapperTest]/[method:debugStateReportsAllFourBankRegisters()] (0 ms)
com.rox.cartridge.Mmc1MapperTest.[engine:junit-jupiter]/[class:com.rox.cartridge.Mmc1MapperTest]/[method:prgBankMode3PreservesNonZeroOffsetWithinTheFixedWindow()] (4 ms)
com.rox.cartridge.Mmc1MapperTest.[engine:junit-jupiter]/[class:com.rox.cartridge.Mmc1MapperTest]/[method:prgRamReadsBackWhatWasWritten()] (0 ms)
com.rox.cartridge.Mmc1MapperTest.[engine:junit-jupiter]/[class:com.rox.cartridge.Mmc1MapperTest]/[method:rejectsZeroLengthPrgRom()] (0 ms)
com.rox.cartridge.Mmc1MapperTest.[engine:junit-jupiter]/[class:com.rox.cartridge.Mmc1MapperTest]/[method:restorePrgRamRejectsTheWrongLength()] (0 ms)

Report generated by PIT 1.22.1

1		package com.rox.cartridge;
2
3		import com.rox.mem.RAM;
4
5		import java.util.LinkedHashMap;
6		import java.util.Map;
7
8		import static com.rox.ByteUtil.BYTE_MASK;
9
10		/**
11		* iNES mapper 1 (MMC1). Every write to {@code $8000-$FFFF} feeds one bit (the value's bit 0) into a
12		* 5-bit serial shift register, LSB first; on the 5th write, the assembled 5-bit value latches into
13		* one of four internal registers, chosen by which address range that 5th write landed in:
14		* {@code $8000-$9FFF} control, {@code $A000-$BFFF} CHR bank 0, {@code $C000-$DFFF} CHR bank 1,
15		* {@code $E000-$FFFF} PRG bank. A write with bit 7 set doesn't shift at all - it immediately resets
16		* the shift register and forces the control register's PRG bank mode to 3 (switch $8000, fix the
17		* last bank at $C000), matching real hardware's power-on/reset state.
18		*
19		* PRG-ROM bank modes (control register bits 2-3): 0 and 1 both mean "switch a 32KB bank at $8000"
20		* (the PRG bank register's bit 0 is ignored - the whole window moves as one 32KB unit); 2 fixes bank
21		* 0 at $8000 and switches a 16KB bank at $C000; 3 switches a 16KB bank at $8000 and fixes the last
22		* bank at $C000 (the reset state). 8KB PRG-RAM at $6000-$7FFF, always writable - this codebase
23		* doesn't model the PRG-RAM chip-enable bit some MMC1 revisions (B2+) add to the PRG bank register.
24		*
25		* CHR (control register bit 4, {@link #CHR_MODE_BIT}): 0 = 8KB mode, one bank switched by
26		* {@link #chrBank0Register()} with its bit 0 ignored (the whole 8KB window moves as one unit,
27		* mirroring how PRG bank modes 0/1 ignore the PRG bank register's own bit 0); 1 = 4KB mode, two
28		* independently-switched 4KB banks, one per CHR bank register. CHR-RAM boards (no CHR-ROM in the
29		* file) get a single fixed 8KB RAM bank instead - real MMC1+CHR-RAM boards don't bank CHR-RAM either,
30		* so the bank registers are simply ignored in that case. Mirroring is read dynamically from the
31		* control register's low 2 bits on every call (0/1 = fixed single-screen lower/upper, 2 = vertical,
32		* 3 = horizontal) - this overrides the iNES header's mirroring bit, real MMC1 hardware behaviour.
33		*
34		* Simplifications: the extended >256KB SUROM/SOROM addressing scheme, which repurposes CHR bank
35		* register bits as extra PRG bank bits, isn't modeled - not needed for any ROM this codebase
36		* currently loads.
37		*/
38		public final class Mmc1Mapper implements Mapper {
39		private static final int PRG_RAM_SIZE = 0x2000;
40		private static final int PRG_ROM_START_ADDRESS = 0x8000;

Mmc1Mapper.java

Mutations

Active mutators

Tests examined